Embodiments of the present invention relate to a mask plate and a manufacturing method thereof.
Among plane panel displays, thin film transistor liquid crystal displays (TFT-LCDs), with the characteristics of low power consumption, low manufacturing cost, free of irradiation and etc, play an important role. As an important component in a TFT-LCD, each of TFTs comprise a gate electrode, a gate insulating layer, a semiconductor layer, a doped semiconductor layer, a source electrode, a drain electrode, and a passivation layer, and are connected with a respective pixel electrode. An early process for manufacturing a TFT comprises a Five-Mask technology. In the recent years, with the development of the TFT manufacturing technology, more and more broadly applied is a Four-Mask process, in which the gate insulating layer, the semiconductor layer, the doped semiconductor layer, the source electrode and the drain electrode are patterned in same one patterning process. Generally, the Four-Mask technology makes use of a gray tone mask or a half tone mask. During forming the gate insulating layer, the semiconductor layer, the doped semiconductor layer, the source/drain electrodes in the Four-Mask process, the gate insulating layer, the semiconductor layer, the doped semiconductor layer, and the source/drain electrode layer are deposited subsequently on a substrate, and then a photoresist layer is applied and the photoresist layer is exposed with a gray tone mask or a half tone mask so as to form a photoresist pattern with a unexposed region, a partially exposed region, and a fully expose region. The region excluding the source electrode, the drain electrode, the data line and the TFT channel are fully exposed, and the source/drain metal layer is etched for example by a wetting method in this fully exposed area. The TFT channel region is partially exposed, and the partially exposed region is subject to an ashing treatment by a dry method so as to remove the photoresist in this region, and the source/drain metal layer and the doped semiconductor layer between the source/drain electrodes are etched so as to form the TFT channel.
FIG. 21 is a schematic view showing the exposing of the TFT channel region by using a conventional gray tone mask. As shown in FIG. 21, two slits are formed in the semi-transparent region of the gray tone mask, the intensity of the transmitted light decreases due to the interference of the light caused by the two slits, so that the photoresist layer on the object substrate 6 is partially exposed, so the partial exposure effect is obtained. Since such two-slit interference is used, the exposure extent at the positions corresponding to the slits is relatively large and the exposure extent at the position between the two slits (i.e., slit bars) is relatively small, and therefore, unevenness appears on the exposed photoresist layer in the channel region and ripple distribution is formed, which greatly increases the difficulties in the subsequent etching. During the etching process, if the portion of the etched layer corresponding to the portion with relative large exposure extent of the photoresist pattern is ensured to be etched, then the portion of the etched layer corresponding to the portion with relative small exposure extent of the photoresist pattern is not be fully etched, bringing about a defect called as gray tone bridge (GT bridge). If the portion of the etched layer corresponding to the portion with relative small exposure extent of the photoresist pattern is ensured to be etched, then the portion of the etched layer corresponding to the portion with relative large exposure extent of the photoresist pattern is overly etched, bringing about a defect called as channel open. Under the condition of the current grey tone mask technology, the GT bridge and the channel open are hard to be avoided at the same time.
FIG. 22 is a schematic view showing a schematic view showing the exposing of the TFT channel region by using a conventional half tone exposure technology. As shown in FIG. 22, in the half tone mask, the semi-transparent region on the substrate wilt be formed with a semi-transparent film 4 (e.g., Cr2O3) with uniform thickness. Since the semi-transparent film is very thin, the light will partially transmit through the semi-transparent film 4 during the exposure, so that the photoresist layer on the object substrate 6 is partially exposed and the partial exposure effect is obtained. The thickness of the semi-transparent film is uniform and the light in the middle portion of the semi-transparent film is transmitted therethrough vertically, so that the intensity of the light here is large, but the intensity of the light at the both two edges is small. Therefore, the exposed photoresist after exposure with the mask is formed into an ellipse shape as shown in FIG. 21. The exposed photoresist layer in the channel region will be formed-with a relatively small tilt angle 8, so that the length of the channel formed in the subsequent etching process with a dry method is increased, which adversely influences and degrades the charging characteristics of the TFT channel.